Method for forming void-free metallization in an integrated circuit
US6455427B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 1999 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Dec 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76882
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metallization structure and method for fabricating such a metallization structure are presented. The present method preferably includes forming a void within a metal layer. The void may have a void pressure level, which is preferably approximately equal to the pressure in a deposition chamber in which the metal layer is arranged when the void is formed. Subsequently, the void may be collapsed by increasing a pressure level outside of the void to a collapsing pressure level significantly above the void pressure level. Increasing a pressure level outside of the void preferably includes increasing a pressure level within the deposition chamber to a collapsing pressure sufficient to collapse the void. A metallization structure formed by such a process may be substantially void-free, even in narrow, high aspect ratio metallization cavities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.