Method and apparatus for a single upset (SEU) tolerant clock splitter
US6456138B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00338
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock splitter circuit for providing a single event upset (SEU) tolerant clock signal to latches in a space-based environment. The clock splitter circuit can include one or more event offset circuit delay circuits. The event offset delay receives a clock signal and generates a delayed clock signal. The event offset delay circuit can generate an inverted clock signal, a delayed inverted clock signal and a pair of intermediate clock signals. The delayed clock signal and inverted delayed clock signal can be delayed by the known duration of single event effects (SEE). The delayed and undelayed clock signals can be passed to an event blocking filter which can block any disturbance in the delayed and/or undelayed clock signals. A synchronizer can synchronize outputs of the event blocking filter prior to or coincident with being passed to corresponding inverting clock drivers. The synchronizers can also insure that the synchronized blocking filter outputs can not be low simultaneously. Intermediate clocks can also be provided corresponding to the inverting clock drivers. Outputs of the inverting clock driver can be a pair of SEU tolerant non-overlapping clock phase signals for driving o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.