Circuit for biasing a bulk terminal of a MOS transistor
US6456150B1 · kind B1 · utility
5Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Sep 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for biasing the bulk terminal of a first MOS transistor having a first terminal connected to a first line set to a first potential, and a second terminal connected to a second line set to a second potential. The biasing circuit includes a second and a third MOS transistors having first terminals connected respectively to the first line and to the second line, second terminals connected to the bulk terminal of the first MOS transistor, and control terminals connected respectively to the second and to the first line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.