Andrea Sacco
24Patents
8h-index
22Co-inventors
75Inventor score
Filing activity: Jan 19, 2000 → Jun 22, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6259635A | Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories | Physics | 132 | Expired |
| US6259632A | Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories | Physics | 73 | Expired |
| US6650173B1 | Programmable voltage generator | Physics | 25 | Expired |
| US6307778A | Non volatile memory with detection of short circuits between word lines | Physics | 19 | Expired |
| US6873551B2 | Apparatus and method for a configurable mirror fast sense amplifier | Physics | 14 | Expired |
| US6504758B2 | Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding | Physics | 13 | Expired |
| US6424121B1 | Voltage generator switching between alternating, first and second voltage values, in particular for programming multilevel cells | Physics | 11 | Expired |
| US6373780B1 | Single supply voltage nonvolatile memory device with row decoding | Physics | 9 | Expired |
| US7599231B2 | Adaptive regulator for idle state in a charge pump circuit of a memory device | Physics | 8 | Active |
| US7184311B2 | Method and system for regulating a program voltage value during multilevel memory device programming | Physics | 6 | Expired |
| US6809961B2 | Regulation method for the drain, body and source terminals voltages in a non-volatile memory cell during a program phase and corresponding program circuit | Physics | 6 | Expired |
| US7283396B2 | System and method for matching resistance in a non-volatile memory | Physics | 5 | Expired |
| US6954102B2 | Fast dynamic mirror sense amplifier with separate comparison equalization and evaluation paths | Physics | 5 | Expired |
| US6456150B1 | Circuit for biasing a bulk terminal of a MOS transistor | Electricity | 5 | Expired |
| US7242242B2 | Fast dynamic low-voltage current mirror with compensated error | Physics | 4 | Expired |
| US7379338B2 | Method and system for regulating a program voltage value during multilevel memory device programming | Physics | 3 | Active |
| US7983098B2 | Adaptive regulator for idle state in a charge pump circuit of a memory device | Physics | 3 | Active |
| US6603681B2 | Method of pulse programming, in particular for high-parallelism memory devices, and a memory device implementing the method | Physics | 3 | Expired |
| US7084699B2 | Fast dynamic low-voltage current mirror with compensated error | Physics | 1 | Expired |
| US11281564B2 | Method and system for generating key performance indicators (KPIs) for software based on debugging information | Physics | 1 | Active |
| US7236050B2 | Fast dynamic low-voltage current mirror with compensated error | Physics | 1 | Expired |
| US7551498B2 | Implementation of column redundancy for a flash memory with a high write parallelism | Physics | 0 | Active |
| US7447071B2 | Low voltage column decoder sharing a memory array p-well | Physics | 0 | Active |
| US7301814B2 | System and method for avoiding offset in and reducing the footprint of a non-volatile memory | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.