Using single lookup table to correct differential non-linearity errors in an array of A/D converters
US6456212B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Mar 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1205
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Generation of a single look-up table for performing DNL correction on an array of analog-to-digital converters (ADCs) is disclosed. Initially, the analog input voltages to the array of ADCs are generated. The input voltages ramp up in steps of some predetermined value. Then, the digital output data are collected and stored in a frame-grabber buffer. A frame of output data are examined for missed codes. The missed codes are identified and recorded. Next, an ADC with a highest number of missed codes is selected for use in generating the look-up table. Finally, the look-up table entries are filled in with consecutive integer values using the corresponding actual output of the selected ADC as an address in the look-up table. During this process, there will be some entries that are missing. These empty entries are filled in with values identical to the value following the empty entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.