Method and apparatus for gating a global column select line with address transition detection
US6456540B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jan 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for a memory device is described. In one embodiment, global Y (GY) enable is gated by the trailing edge of a address transition detection (ATD) pulse. The ATD pulse ensures that the GY enable is off during periods when the memory device is not attempting to read a memory cell. The sense (SEN) node between the GY transistor and drain bias circuit may be charged up and global bit line (GBL) may be grounded. During this time, the power supply current is cut off by the GY transistor itself, thereby eliminating the need of separate cut-off transistors within the drain bias circuit. This permits minimal time delay in sensing after the incoming address is stable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.