Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration
US6456553B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Jul 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit configuration for switching over a receiver circuit, in particular in DRAM memories, between a standby mode and an operating mode, includes a differential amplifier functioning as a receiver receiving a control voltage derived from a reference current and generated or fed in for setting a correct operating point of said differential amplifier. A line feeds a current for generating the control voltage. Switching elements are disposed in said line for each receiver. The switching elements are permanently closed in the operating mode by an enable signal present at said switching elements for continuously supplying the current for generating the control voltage. The switching elements are closed at discrete times or periodically in the standby mode by feeding a refresh signal for discontinuously refreshing the control voltage. A DRAM memory having the circuit configuration is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.