Iterative prediction of circuit delays
US6457160B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2000 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Nov 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a technique for circuit delay prediction in which blocks (preferably, non-overlapping blocks) are specified, each of the blocks including a portion of the circuit. Delay calculation collars (DCCs) are then defined for the blocks, the DCCs including complete dependency information required to calculate delay within the blocks. Next, delay is calculated for the blocks based on the DCCs and delay is calculated for the circuit based on the DCCs. The DCCs are then modified as necessary based on results of either or both of the delay calculation for the blocks or the circuit. The delay calculation and DCC modification steps are then repeated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.