Multi-chip semiconductor package structure
US6458617B1 · kind B1 · utility
27Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Feb 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.