Semiconductor chip package and method of fabricating same
US6458627B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 1999 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Oct 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface of the semiconductor chip such that through-holes in the thermosetting resin expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin and at least on of the multi-layer wiring pattern and the connecting unit, such that at least one through-hole in the solder resist exposes a portion of at least one of the multi-layer wiring pattern and the connecting unit; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the at least one of the multi-wiring pattern and the connecting unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.