Method for manufacturing a multilayer interconnection structure
US6458690B2 · kind B2 · utility
4Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Jul 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a multilayer interconnection structure on a wafer by using a damascene technique includes the steps of separating the area of the wafer into a peripheral area, an intermediate area and a central area as viewed from the outer periphery toward the center of the wafer. The lower-level interconnections having a smaller width are formed in the intermediate and central areas, whereas the upper-level interconnections having a larger width are formed in the central area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.