Plated through hole interconnections
US6458696B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Apr 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/423
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The specification describes interconnection techniques for interconnecting large arrays of micromechanical devices on a silicon platform. Interconnections are routed through vias extending through the thickness of the substrate. The vias are formed by etching holes through the silicon wafer, depositing an insulating layer on the sidewalls of the holes, depositing a barrier layer on the insulating layer, electrolytically depositing a metal selected from the group consisting of copper and nickel to form via plugs in the holes, and depositing another barrier layer over the via plugs. It is found that electrolytic deposition will successfully plug the holes even when the aspect ratio of the through holes is greater than four and the hole diameter less than 100 microns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.