Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
US6459150B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A single-step bumping/bonding method for forming a semiconductor package of two electronic substrates electrically connected together by solder bumps. In the method, a first electronic substrate is provided equipped with a first plurality of conductive pads formed in an insulating material layer, the plurality of conductive pads each having an aperture formed therethrough for receiving a solder material when the first electronic substrate is positioned juxtaposed to a second electronic substrate equipped with a second plurality of conductive pads such that solder bumps may be formed bonding the first plurality of conductive pads to the second plurality of conductive pads. One of the two electronic substrates may be a silicon wafer, while the other may be a printed circuit board or a silicon wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.