Encapsulated semiconductor die package
US6459162B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Mar 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die package has a lead frame, a die attached to the lead frame and an encapsulant enclosing the lead frame and the die. The distance between the top outside face of the encapsulant and the frame is substantially equal to the distance between the bottom outside face of the encapsulant and the die, and the distance between the top outside face of the encapsulant and the frame is substantially two and half times the distance between the bottom outside face of the encapsulant and the lead frame. Consequently, the different thickness of different encapsulant portions achieves an optimum balance during curing that effectively reduces the deformation of the encapsulant. In addition, the encapsulant can be completely formed by an injection process, and no crack will form in the encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.