Twin MONOS memory cell usage for wide program
US6459622B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2002 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Mar 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of memory cell selection and operation to obtain wide program bandwidth and EEPROM erase capability. Two storage sites within a memory cell can be simultaneously selected during read, program and erase. By proper biasing, each of the sites can be independently read and programmed. Also, during program, the source of energy to produce the current flow can be dynamically obtained from the stored charge on the selected bit line. If the bit line capacitance is not adequate to provide a charge that is necessary, additional bit line capacitance is borrowed from unselected bit lines, or a source follower select transistor may be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.