Three metal process for optimizing layout density
US6459625B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2001 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Jan 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method and system to optimize electrical interconnection of electrical components in a periphery area of a memory device thereby minimizing the periphery area. The periphery area is divided into a plurality of sub-circuits formed by selectively electrically connecting the electrical components. Electrical interconnection of the electrical components to form the sub-circuits is accomplished using a first metal layer and a second metal layer. The first metal layer is formed to create a plurality of first metal layer lines that are oriented to extend in substantially one direction on the memory device. The second metal layer is formed to create a plurality of second metal layer lines that are oriented to extend substantially perpendicular to the first metal layer lines. The plurality of sub-circuits are electrically interconnected using a third metal layer that is formed to create a plurality of third metal layer lines that are oriented to extend substantially parallel to the first metal layer lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.