2-dimensional discrete cosine transform using a polynomial transform
US6460061B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement and method for performing the 2-D DCT. An input permutation processor reorders input samples, constructing a logical matrix of input samples. A plurality of 1-D DCT processors are arranged to receive the reordered data and apply the 1-D DCT along extended diagonals of the matrix. The output polynomials from the 1-D DCT processors are provided to a polynomial transform processor, and the output data from the polynomial transform processor are reordered, by an output permutation processor. The 1-D DCT processors and polynomial transform are multiplier free, thereby minimizing usage of FPGA resources in an FPGA implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.