Network processor, memory organization and methods
US6460120B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1999 |
| Grant date | Oct 1, 2002 |
| Priority date | — |
| Expiry date | Aug 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.