Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making the device
US6461916B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Feb 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.