Power MOS device with improved gate charge performance
US6461918B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.