Semiconductor trench isolation process that utilizes smoothening layer
US6461932B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 1998 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Dec 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trenched-isolated semiconductor structure is created by a process that entails forming a patterned trench (54) along an upper surface of a semiconductor body (40). A dielectric layer (56) is provided over the upper semiconductor surface. The dielectric layer is covered with a smoothening layer (60) whose upper surface is smoother than the upper surface of the dielectric layer. The smoothening layer is removed starting from its upper surface. During the removal of the smoothening layer, upward-protruding material of the dielectric layer progressively becomes exposed and is also removed. As a result, the remainder of dielectric layer has a smoother upper surface than the initial upper surface of the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.