Semiconductor package with central circuit pattern
US6462283B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1999 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Sep 3, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49169
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A printed wired board is provided, in which an area for extracting lines for plating of the printed wired board is made small and at the same time the number of the extracting lines for plating within a packaging area is made small, resulting in an improvement of wiring efficiency. The circuit pattern formed on an insulating film has a window portion and is not formed toward the periphery of the insulating film, and a bonding pad is electroplated, where the bonding pads are to be connected with a center-pad of a semiconductor by a bonding wire through the window portion. Accordingly, even when the shrinkage of semiconductor packages or narrow ball pitch is forwarded, the degree of freedom of drawing of circuit pattern in the printed wired board can be made large.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.