Contact member stacking system and method
US6462408B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Mar 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for selectively stacking and interconnecting individual integrated circuit devices to create a high-density integrated circuit module. In a preferred embodiment, conventional thin small outline packaged (TSOP) memory circuits are vertically stacked one above the other. The constituent IC elements act in concert to provide an assembly of memory capacity approximately equal to the sum of the capacities of the ICs that constitute the assembly. The IC elements of the stack are electrically connected through individual contact members that connect corresponding leads of IC elements positioned adjacently in the stack. In a preferred embodiment, the contact members are composed of lead frame material. Methods for creating stacked integrated circuit modules are provided that provide reasonable cost, mass production techniques to produce modules. In a preferred method, a carrier frame of lead frame material is configured to present an opening into which opening project plural lead-like contact members that correspond to the leads of an IC element. The contact members contact the leads of the lower IC element of the stack while the leads of the upper IC of the assembly co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.