Barrier pad for wafer level chip scale packages
US6462426B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Dec 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device comprising a semiconductor die having a plurality of conductive pads. Over the conductive pads is formed a passivation layer that has a plurality of passivation layer openings. The passivation layer openings are positioned over an associated one of the conductive pads. Barrier base pads are placed in electrical contact with the conductive pads such that a portion of each of barrier base pads cover at least the perimeter of each passivation layer opening. Each of the barrier base pads prevents cracks from propagating through the integrated circuit device. In another aspect of the invention, the integrated circuit device is attached to an external substrate by connecting the contact bumps to the bond pads on an electronic substrate. In yet another aspect of the invention, a method for manufacturing the integrated circuit device is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.