Digitally programmable phase-lock loop for high-speed data communications
US6462594B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2000 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices. Accordingly, the present inventors devised a digitally programmable phase-lock loop which operates at a frequency selected from a set of two of more frequencies. One such phase-lock loop include…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.