Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array
US6462984B1 · kind B1 · utility
188Cited by
19References
20Claims
0Family size
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Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Jun 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) has a number of memory cells, each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell. A target memory cell of the IC is programmed while simultaneously floating a number of unselected bitlines and wordlines in the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.