Method to arbitrate for a cache block
US6463514B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1998 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | May 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0857
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more subarray selection bits in each of the first and second cache addresses, and further preferably includes a common contention logic unit for both the first and second cache access circuits. The first cache address is retained within the first cache access circuit so that the first cache access circuit does not need to re-generate the first cache address. If the same word (or doubleword) is being accessed by multiple load operations, this condition is not considered contention and both operations are allowed to proceed, even though they are in the same subarray of the interleaved cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.