Dual on-chip and in-package clock distribution system
US6463547B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1999 |
| Grant date | Oct 8, 2002 |
| Priority date | — |
| Expiry date | Dec 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.