Inventor · Portsmouth, GB

Daniel W. Bailey

39Patents
9h-index
41Co-inventors
75Inventor score

Filing activity: Jul 6, 1981 → Apr 10, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US6473334B1 Multi-ported SRAM cell with shared bit and word lines and separate read and write ports Physics 35 Expired
US7392414B2 Method, system, and apparatus for improving multi-core processor performance Emerging Cross-Sectional Technologies 32 Expired
US7301373B1 Asymmetric precharged flip flop Electricity 21 Expired
US4428508A Athletes water bottle Human Necessities 18 Expired
US6463547B1 Dual on-chip and in-package clock distribution system Physics 18 Expired
US7509518B2 Determining the impact of a component failure on one or more services Emerging Cross-Sectional Technologies 17 Active
US8072252B2 Compound logic flip-flop having a plurality of input stages Electricity 15 Active
US7389440B2 Method, system, and apparatus for improving multi-core processor performance Emerging Cross-Sectional Technologies 11 Expired
US9606177B2 Scan flip-flop circuit with dedicated clocks Physics 9 Active
US7737752B2 Techniques for integrated circuit clock management Electricity 7 Active
US8014485B2 Techniques for integrated circuit clock management using multiple clock generators Electricity 6 Active
US11005649B2 Autonomous driving controller encrypted communications Electricity 6 Active
US6463548B1 Method and apparatus to enforce clocked circuit functionality at reduced frequency without limiting peak performance Physics 5 Expired
US9680450B2 Flip-flop circuit with latch bypass Electricity 5 Active
US6400186B1 Settable digital CMOS differential sense amplifier Physics 5 Expired
US7788519B2 Method, system, and apparatus for improving multi-core processor performance Emerging Cross-Sectional Technologies 5 Active
US7567135B2 Power monitoring device and methods thereof Electricity 4 Active
US8415972B2 Variable-width power gating module Emerging Cross-Sectional Technologies 4 Active
US7681099B2 Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test Physics 4 Active
US7921318B2 Techniques for integrated circuit clock management using pulse skipping Physics 3 Active
US7079615B2 Expanded comparator for control of digital delay lines in a delay locked loop or phase locked loop Electricity 3 Expired
US6107839A High input impedance, strobed CMOS differential sense amplifier with double fire evaluate Physics 3 Expired
USD904769S1 Frame General 2 Active
US10802929B2 Parallel processing system runtime state reload Physics 2 Active
US6529044B2 Conditional clock gate that reduces data dependent loading on a clock network Electricity 2 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.