Semiconductor wafer dividing method
US6465158B1 · kind B1 · utility
129Cited by
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5Claims
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Assignee
Inventor
Key dates
| Filing date | Oct 19, 2000 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Nov 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/78
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer dividing method for dividing a semiconductor wafer, on whose face side many rectangular areas are demarcated by streets arranged in a lattice fashion, along the streets to convert each of the many rectangular areas into a semiconductor chip. In this method, a resist is formed on the face side of the semiconductor wafer. Then, the resist is physically removed in areas extending along the streets. Then, an etching process is applied to the semiconductor wafer to etch the semiconductor wafer along the streets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.