Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing
US6465322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1998 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Jan 15, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.