Method for forming semiconductor integrated circuit microelectronic fabrication having multiple gate dielectric layers with multiple thicknesses
US6465323B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Jul 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Within a method for forming a series of gate dielectric layers having a plurality of thicknesses upon a semiconductor substrate, there is sequentially selectively stripped only a series of sacrificial gate dielectric layers only in locations where new gate dielectric layers are desired to be formed, rather masking a only a portion of a partially sacrificial gate dielectric layer which is desired to be retained and stripping a sacrificial remainder of the gate dielectric layer. By employing the sequential selective stripping method, a semiconductor integrated circuit microelectronic fabrication is formed with enhanced reliability insofar as there is attenuated over etching into isolation regions which separate active regions of a semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.