Semiconductor wafer manufacturing method
US6465328B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Mar 27, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/928
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
An edge-rounded portion mirror finishing process, which results in low deformation on a wafer, which has undergone a slicing process including a grinding process in which double-sided grinding is performed on the. sliced wafer; a finishing grinding process in which high-precision and low-deformation finish grinding is performed on the wafer; an edge rounding process in which low-deformation grinding is performed on an edge-rounded portion of the wafer; a two-sided primary polishing process in which primary polishing is performed on both sides of the edge-rounded wafer; a one-sided finish polishing process in which finish polishing is performed on one side of the wafer that has been primary polished on both sides; and a process in which finish polishing is performed on the edge-rounded portion of the above-mentioned wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.