Integrated circuit package having partially exposed conductive layer
US6465882B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2000 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Jul 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package such as a BGA package for use with an integrated circuit chip. The integrated circuit package has substrate with a cavity that exposes a lower conductive level in the package so that connections between the integrated circuit chip and the lower conductive level may be formed to reduce the through holes formed in the substrate. As a result, additional signal line interconnections may be included in the substrate circuit package and/or the size of the integrated circuit chip may be decreased. Each of these may be implemented for enhanced electrical performance. The multiple wire bonding tiers in the substrate may also provide greater wire separation that eases wire bonding and subsequent encapsulation processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.