Clock enable control circuit for flip flops
US6466049B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Sep 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock enable control circuit for controlling flip flops on a programmable logic device. The clock enable control circuit either passes an original data signal to the input terminal of a flip flop, or feeds back an output signal from the output terminal to the input terminal of the flip flop in response to a clock enable control signal. The clock enable control signal is selected from one of a set control signal and a reset control signal that are otherwise provided on the programmable logic device to selectively control set and reset functions of the flip flop. In one embodiment, the set and reset control signals are generated as product-term signals that are programmably routed by a product-term allocator circuit to a macrocell including the flip flop and the clock enable control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.