Data coding for multi-bit-per-cell memories having variable numbers of bits per memory cell
US6466476B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Feb 11, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-bit-per-cell non-volatile memory stores different portions of a data stream using different numbers of bits per cell. In particular, data that requires a high degree of data integrity (e.g., the header of a data frame) is stored using a relatively small number of bits per memory cell. Data that is more error-tolerant (e.g., the main data representing music, images, or video) is stored using a relatively large number of bits per memory cell. Write circuitry decodes an input data stream and determines the number of bits to be written in each memory cell. Read circuitry decodes an output data stream and determines a number of bits read from each memory cell to generate the data stream. One such memory includes a decoder in the write circuitry and a decoder in the read circuitry, and another embodiment includes a single decoder that the write and read circuits share. The decoder can include programmable logic array that a user can program according to a protocol used in the data stream to be recorded in and played back from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.