Device and method for programming nonvolatile memory cells with automatic generation of programming voltage
US6466481B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1999 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Nov 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.