Semiconductor memory device having a column select line transmitting a column select signal
US6466509B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 18, 2002 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Jan 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.