Controlled reissue delay of memory requests to reduce shared memory address contention
US6467032B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 1999 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Jun 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a shared memory system, a plurality of requesters issue requests for particular memory addresses over a system bus. Requests, if denied, are later reissued after a controlled reissue delay. The reissue delay for a particular request is controllably varied in response to the number of requests being issued by requesters other than that which issued the request. Typically, the number of requests issued by other requesters for a common memory address as the particular request is tracked, and the reissue delay is controllably increased as the number of such requests increases. As such, the frequency that requests for highly contended memory addresses (which are more likely to be denied) is decreased relative to requests for less contended addresses, thereby freeing bandwidth on the system bus for requests that are more likely to be granted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.