Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology

US6468849B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Taylor R. Efland · Richardson, US
• Alec J. Morton · Plano, US
• Chin-Yu Tsai · Plano, US

Key dates

• Filing date: Jun 8, 2000
• Grant date: Oct 22, 2002
• Expiry date: Jun 8, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.