Semiconductor package and mount board
US6469393B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Apr 14, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The package-side land 3a of a semiconductor package P1 is wholly exposed into the opening 5a of a solder resist layer 5. The board-side land 12a of the mount board B1 is also wholly exposed into the opening 13a of a solder resist layer 13. When the semiconductor package P1 and the mount board B1 are joined to each other through a soldering layer 14a, the soldering layer 14a is brought into contact to both the lands 3a and 12a while extending to the side wall surfaces thereof so that the joint strength can be enhanced by the increasing contact area and the shape. When the lands 3a and 12a are set to be equal to each other in dimension and shape, the soldering layer 14a is shaped into a pillar having a substantially uniform section, thereby preventing local concentration of stress. To ensure the joint strength based on a conductive material layer and enhance the mount reliability by making fine the terminals on a relay substrate which correspond to the input or output terminals of a semiconductor chip, and making the pitch narrow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.