Memory architecture with refresh and sense amplifiers
US6469924B2 · kind B2 · utility
4Cited by
3References
1Claims
0Family size
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Inventor
Key dates
| Filing date | May 14, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | May 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.