Structure and method for high speed sensing of memory arrays
US6469929B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Aug 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for sensing the state of a memory cell includes both dynamic and static clamping of the bit line coupled to a memory cell. This dual clamping configuration/operation ensures a quick charge of the bit line while eliminating overcharging of the bit line. Thus, sensing the state of the memory cell is substantially independent of the size of the memory array. A sensing system for sensing the state of a memory cell can include a system bit line coupled to a terminal of the memory cell, a charge initiation device for activating a charge operation on the system bit line, and a control unit connected between the system bit line and the charge initiation device. The control unit includes a static clamp to charge the system bit line to a first predetermined voltage and a dynamic clamp to charge the system bit line to a second predetermined voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.