Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read data
US6470431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Apr 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.