Methods and apparatus for reducing false hits in a non-tagged, n-way cache
US6470438B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, each data value which is provided to a non-tagged, n-way cache is hashed with a number of bits which correspond to the data value, thereby producing a hashed data value. Preferably, the bits which are hashed with the data value are address bits. The hashed data value is then written into one or more ways of the cache using index hashing. A cache hit signal is produced using index hashing and voting. In a cache where data values assume only a few different values, or in a cache where many data values which are written to the cache tend to assume a small number of data values, data hashing helps to reduce false hits by insuring that the same data values will produce different hashed data values when the same data values are associated with different addresses. In another embodiment of the invention, data values which are provided to a non-tagged, n-way cache are written into the cache in a non-count form. Whereas a counter tends to quickly saturate to one extreme or the other (e.g., all zeros or all ones), or briefly take on a value which approaches an extreme, a non-count data value (e.g., branch prediction history bits) tend to assume a wider var…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.