Parallel test circuit of semiconductor memory device
US6470465B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Dec 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel test circuit for a semiconductor memory device includes a divided output driver configuration capable of generating a tri-state output. The parallel test circuit has a main output driver for outputting a signal having a first level when cell arrays are stored with data having the same level, and a sub output driver for outputting a signal having an intermediate level when the cell arrays are stored with data having different levels. Because the parallel test circuit can accurately detect errors, it can perform a reliable parallel test for pass/fail devices, and can be used to check device characteristics or for a speed sort test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.