Synthesizable synchronous static RAM
US6470475B2 · kind B2 · utility
11Cited by
3References
36Claims
0Family size
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Inventor
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Nov 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synthesizable, synchronous static RAM may include custom built memory cells and a semi-custom input/output/precharge section in bit slice form, a semi-custom built decoder connected to the bit slice, and a semi-custom built control clock generation section connected to the semi-custom built decoder and input/output section. The components may be arranged to provide high speed access, easy testability, and asynchronous initialization capabilities while reducing design time, and in a size that is significantly smaller than existing semi-custom or standard cell based memory designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.