Semiconductor temperature monitor
US6472232B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/21
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method, and associated structure, for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across the wafer surface. Given a substrate that includes a semiconductor material and a first dopant, an amorphous layer is formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. The amorphous layer may be formed by directing an ionic species, such as ionic germanium, into the top portion of the substrate. Alternatively, particular second dopants, such as arsenic, may serve to also amorphize the top portion of the substrate. Next, the wafer is heated to a temperature in a range of 450 to 625° C. The heating of the wafer recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the recrystallized layer, a spatial distribution of sheet resistance over the wafer surfac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.