Double gate trench transistor

US6472258B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James W. Adkisson · Jericho, US
• Paul D. Agnello · Wappingers Falls, US
• Arne Ballantine · Palo Alto, US
• Rama Divakaruni · Ossining, US
• Erin C. Jones · Yorktown Heights, US
• Jed H. Rankin · South Burlington, US

Key dates

• Filing date: Nov 13, 2000
• Grant date: Oct 29, 2002
• Expiry date: Dec 28, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6739

Abstract

A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.