Methods for improved encapsulation of thick metal features in integrated circuit fabrication
US6472307B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jan 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of manufacturing an integrated circuit having a capping layer over a thick metal feature. In one embodiment, the method comprises forming first and second oxide layers over the thick metal feature, forming a composite oxide layer including an oxide spacer by etching the first and second oxide layers, and forming a capping layer over the composite oxide layer. More specifically, forming the first oxide layer involves using a high density plasma (HDP) process, forming the second oxide layer involves using a plasma enhanced chemical vapor deposition (PECVD) process, and forming the composite oxide layer preferably involves etching with a reactive ion etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.